1. Field of the Invention
The present invention relates to a comparator circuit that is mounted to a semiconductor device.
2. Description of the Related Art
FIG. 5 is a circuit diagram showing a conventional comparator circuit. FIG. 6 is a timing chart showing an on/off operation of a conventional switch.
An input terminal of the comparator circuit is connected to an inverting input terminal of a first amplifier 11 having gain a through a switch 14 and an input capacitor 10. A connection point of the switch 14 and the input capacitor 10 is grounded through a switch 15. A noninverting input terminal of the first amplifier 11 is grounded. An output terminal of the first amplifier 11 is connected to an output terminal of the comparator circuit through a latch circuit 13. Also, an output terminal of the first amplifier 11 is connected to the inverting input terminal of the first amplifier 11 through a switch 16.
The on/off operation of the switches 14 and 16 is controlled according to a clock signal Φ1 shown in FIG. 6, the on/off operation of the switch 15 is controlled according to a clock signal Φ2, and the latch circuit 13 amplifies a voltage at the output terminal of the first amplifier 11 according to the clock signal Φ2.
Next, a description will be given of the operation of the sampling state of a conventional comparator circuit. FIG. 7 is a circuit diagram showing the sampling state of the conventional comparator circuit.
When the clock signal Φ1 becomes high and the clock signal Φ2 becomes low, the comparator circuit becomes the circuit shown in FIG. 7, and is brought into a sampling state. An input voltage Vin at the input terminal of the comparator circuit is sampled to the input capacitor 10.
Now, it is assumed that, in the sampling state, a voltage at the inverting input terminal of the first amplifier 11 is XN1, a voltage at the output terminal of the first amplifier 11 is Vo1, an amplification gain of the first amplifier 11 is a, an input voltage at the input terminal of the comparator circuit is Vin, an offset voltage is VOFF, and electric charges in the input capacitor 10 are Q1. Then, XN1 is represented as follows.XN1=a(0−XN1+VOFF)  (1)XN1=[a/(1+a)]VOFF  (2)
Also, Q1 is represented as follows.Q1=C(XN1−Vin)=C[[a/(1+a)]VOFF−Vin]  (3)
Next, a description will be given of an operation of a hold and compare state of the conventional comparator circuit. FIG. 8 is a circuit diagram showing the hold and compare state of the conventional comparator circuit.
When the clock signal Φ2 becomes high and the clock signal Φ1 becomes low, the comparator circuit becomes the circuit shown in FIG. 8 and is brought in a hold and compare state. The input terminal of the comparator circuit is grounded, and the input voltage Vin that has been sampled to the input capacitor 10 is compared by the first amplifier 11 and then input to the latch circuit 13.
Now, it is assumed that, in the hold and compare state, a voltage at the inverting input terminal of the first amplifier 11 is XN2, a voltage at the output terminal of the first amplifier 11 is Vo2, and the electric charges in the input capacitor 10 are Q2. Then, Q2 is represented as follows.Q2=C(XN2−0)=CXN2  (4)
Q1 is equal to Q2 according to the law of conservation of charge, so XN2 is represented as follows.Q2=CXN2=Q1=C[[a/(1+a)]VOFF−Vin]  (5)XN2=[a/(1+a)]VOFF−Vin  (6)
Also, Vo2 is represented as follows.Vo2=a(0−XN2+VOFF)  (7)
When Expression (6) is substituted for Expression (7), Vo2 is represented as follows.Vo2=aVin+[a/(1+a)]VOFF  (8)
Vo2 in Expression (8) is input to the latch circuit 13, then greatly amplified in synchronization with the clock signal Φ2, and latched.
Further, there has been known a comparator circuit having an offset adjustment terminal (for example, refer to JP07-092204 A).
In the conventional comparator circuit, when an attempt is made to sufficiently cancel the offset voltage VOFF of the first amplifier 11, it is necessary to increase the amplification gain a.
However, in the case where the frequencies of the clock signals Φ1 and Φ2 are made high so as to operate the first amplifier 11 at a high speed, the operation of the first amplifier 11 does not follow the frequencies. As a result, the amplification gain a is lowered. When the amplification gain a is lowered, there arises a problem such that the offset voltage VOFF is insufficiently cancelled as represented by Expression (8).